High performance embedded architectures and compilers : third international conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008 : proceedings /
High performance embedded architectures and compilers : third international conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008 : proceedings /
HiPEAC 2008
Per Stenström [and others] (eds.).
- Berlin ; New York : Springer, 2008.
- 1 online resource (xiii, 400 pages) : illustrations
- Lecture notes in computer science, 4917 0302-9743 ; LNCS sublibrary. SL 1, Theoretical computer science and general issues .
- Lecture notes in computer science ; 4917. LNCS sublibrary. SL 1, Theoretical computer science and general issues. .
Includes bibliographical references and index.
Invited Program -- Supercomputing for the Future, Supercomputing from the Past (Keynote) -- I Multithreaded and Multicore Processors -- MIPS MT: A Multithreaded RISC Architecture for Embedded Real-Time Processing -- rMPI: Message Passing on Multicore Processors with On-Chip Interconnect -- Modeling Multigrain Parallelism on Heterogeneous Multi-core Processors: A Case Study of the Cell BE -- IIa Reconfigurable -- ASIP -- BRAM-LUT Tradeoff on a Polymorphic DES Design -- Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array -- Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP -- IIb Compiler Optimizations -- Fast Bounds Checking Using Debug Register -- Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis -- An Experimental Environment Validating the Suitability of CLI as an Effective Deployment Format for Embedded Systems -- III Industrial Processors and Application Parallelization -- Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length Instructions -- Experiences with Parallelizing a Bio-informatics Program on the Cell BE -- Drug Design Issues on the Cell BE -- IV Power-Aware Techniques -- Coffee: COmpiler Framework for Energy-Aware Exploration -- Integrated CPU Cache Power Management in Multiple Clock Domain Processors -- Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation -- V High-Performance Processors -- The Significance of Affectors and Affectees Correlations for Branch Prediction -- Turbo-ROB: A Low Cost Checkpoint/Restore Accelerator -- LPA: A First Approach to the Loop Processor Architecture -- VI Profiles: Collection and Analysis -- Complementing Missing and Inaccurate Profiling Using a Minimum Cost Circulation Algorithm -- Using Dynamic Binary Instrumentation to Generate Multi-platform SimPoints: Methodology and Accuracy -- Phase Complexity Surfaces: Characterizing Time-Varying Program Behavior -- VII Optimizing Memory Performance -- MLP-Aware Dynamic Cache Partitioning -- Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture -- Code Arrangement of Embedded Java Virtual Machine for NAND Flash Memory -- Aggressive Function Inlining: Preventing Loop Blockings in the Instruction Cache.
This book constitutes the refereed proceedings of the Third International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2008, held in Göteborg, Sweden, January 27-29, 2008. The 25 revised full papers presented together with 1 invited keynote paper were carefully reviewed and selected from 77 submissions. The papers are organized in topical sections on Multithreaded and Multicore Processors, Reconfigurable - ASIP, Compiler Optimizations, Industrial Processors and Application Parallelization, Power-Aware Techniques, High-Performance Processors, Profiles: Collection and Analysis as well as Optimizing Memory Performance.
9783540775607 3540775609 9783540775591 3540775595 1281179825 9781281179821 9788354077565 835407756X
10.1007/978-3-540-77560-7 doi
12212101
978-3-540-77559-1 Springer http://www.springerlink.com
2007942570
08,N03,0040 dnb
DE-101 014515561 Uk 986860662 GyFmDB
Embedded computer systems--Congresses.
Compilers (Computer programs)--Congresses.
Computer architecture--Congresses.
Systèmes enfouis (Informatique)--Congrès.
Compilateurs (Logiciels)--Congrès.
Ordinateurs--Architecture--Congrès.
Informatique.
Compilers (Computer programs)
Computer architecture.
Embedded computer systems.
wiskunde mathematics datacommunicatie data communication ontwerp design computerwetenschappen computer sciences computernetwerken computer networks procesarchitectuur process architecture programmeertalen programming languages Information and Communication Technology (General) Informatie- en communicatietechnologie (algemeen)
Congress
Conference papers and proceedings.
Conference papers and proceedings.
Actes de congrès.
TK7895.E42 / H57 2008eb
004.2/2
Includes bibliographical references and index.
Invited Program -- Supercomputing for the Future, Supercomputing from the Past (Keynote) -- I Multithreaded and Multicore Processors -- MIPS MT: A Multithreaded RISC Architecture for Embedded Real-Time Processing -- rMPI: Message Passing on Multicore Processors with On-Chip Interconnect -- Modeling Multigrain Parallelism on Heterogeneous Multi-core Processors: A Case Study of the Cell BE -- IIa Reconfigurable -- ASIP -- BRAM-LUT Tradeoff on a Polymorphic DES Design -- Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array -- Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP -- IIb Compiler Optimizations -- Fast Bounds Checking Using Debug Register -- Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis -- An Experimental Environment Validating the Suitability of CLI as an Effective Deployment Format for Embedded Systems -- III Industrial Processors and Application Parallelization -- Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length Instructions -- Experiences with Parallelizing a Bio-informatics Program on the Cell BE -- Drug Design Issues on the Cell BE -- IV Power-Aware Techniques -- Coffee: COmpiler Framework for Energy-Aware Exploration -- Integrated CPU Cache Power Management in Multiple Clock Domain Processors -- Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation -- V High-Performance Processors -- The Significance of Affectors and Affectees Correlations for Branch Prediction -- Turbo-ROB: A Low Cost Checkpoint/Restore Accelerator -- LPA: A First Approach to the Loop Processor Architecture -- VI Profiles: Collection and Analysis -- Complementing Missing and Inaccurate Profiling Using a Minimum Cost Circulation Algorithm -- Using Dynamic Binary Instrumentation to Generate Multi-platform SimPoints: Methodology and Accuracy -- Phase Complexity Surfaces: Characterizing Time-Varying Program Behavior -- VII Optimizing Memory Performance -- MLP-Aware Dynamic Cache Partitioning -- Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture -- Code Arrangement of Embedded Java Virtual Machine for NAND Flash Memory -- Aggressive Function Inlining: Preventing Loop Blockings in the Instruction Cache.
This book constitutes the refereed proceedings of the Third International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2008, held in Göteborg, Sweden, January 27-29, 2008. The 25 revised full papers presented together with 1 invited keynote paper were carefully reviewed and selected from 77 submissions. The papers are organized in topical sections on Multithreaded and Multicore Processors, Reconfigurable - ASIP, Compiler Optimizations, Industrial Processors and Application Parallelization, Power-Aware Techniques, High-Performance Processors, Profiles: Collection and Analysis as well as Optimizing Memory Performance.
9783540775607 3540775609 9783540775591 3540775595 1281179825 9781281179821 9788354077565 835407756X
10.1007/978-3-540-77560-7 doi
12212101
978-3-540-77559-1 Springer http://www.springerlink.com
2007942570
08,N03,0040 dnb
DE-101 014515561 Uk 986860662 GyFmDB
Embedded computer systems--Congresses.
Compilers (Computer programs)--Congresses.
Computer architecture--Congresses.
Systèmes enfouis (Informatique)--Congrès.
Compilateurs (Logiciels)--Congrès.
Ordinateurs--Architecture--Congrès.
Informatique.
Compilers (Computer programs)
Computer architecture.
Embedded computer systems.
wiskunde mathematics datacommunicatie data communication ontwerp design computerwetenschappen computer sciences computernetwerken computer networks procesarchitectuur process architecture programmeertalen programming languages Information and Communication Technology (General) Informatie- en communicatietechnologie (algemeen)
Congress
Conference papers and proceedings.
Conference papers and proceedings.
Actes de congrès.
TK7895.E42 / H57 2008eb
004.2/2