Advances in computer systems architecture : (Record no. 637542)

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007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION
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fixed length control field 081017s2005 gw a ob 101 0 eng d
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National bibliography number 05,A47,0010
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015 ## - NATIONAL BIBLIOGRAPHY NUMBER
National bibliography number 05,N43,0016
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Record control number 976544016
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020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9783540321088
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 354032108X
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 3540296433
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9783540296430
024 3# - OTHER STANDARD IDENTIFIER
Standard number or code 9783540296430
028 52 - PUBLISHER NUMBER
Publisher number 11572961
029 1# - (OCLC)
OCLC library identifier AU@
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037 ## - SOURCE OF ACQUISITION
Stock number 978-3-540-29643-0
Source of stock number/acquisition Springer
Note http://www.springerlink.com
050 #4 - LIBRARY OF CONGRESS CALL NUMBER
Classification number QA76.9.A73
Item number A28 2005eb
072 #7 - SUBJECT CATEGORY CODE
Subject category code QA
Source lcco
072 #7 - SUBJECT CATEGORY CODE
Subject category code COM
Subject category code subdivision 011000
Source bisacsh
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 004.22
Edition number 22
084 ## - OTHER CLASSIFICATION NUMBER
Classification number 54.31
Number source bcl
049 ## - LOCAL HOLDINGS (OCLC)
Holding library MAIN
111 2# - MAIN ENTRY--MEETING NAME
Meeting name or jurisdiction name as entry element ACSAC (Asia-Pacific Computer Systems Architecture Conference)
Number of part/section/meeting (10th :
Date of meeting 2005 :
Location of meeting Singapore)
9 (RLIN) 28245
245 10 - TITLE STATEMENT
Title Advances in computer systems architecture :
Remainder of title 10th Asia-Pacific conference, ACSAC 2005, Singapore, October 24-26, 2005 : proceedings /
Statement of responsibility, etc. Thambipillai Srikanthan, Jingling Xue, Chip-Hong Chang (eds.).
246 30 - VARYING FORM OF TITLE
Title proper/short title ACSAC 2005
260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT)
Place of publication, distribution, etc. Berlin ;
-- New York :
Name of publisher, distributor, etc. Springer,
Date of publication, distribution, etc. 2005.
300 ## - PHYSICAL DESCRIPTION
Extent 1 online resource (xvii, 833 pages) :
Other physical details illustrations
336 ## - CONTENT TYPE
Content type term text
Content type code txt
Source rdacontent
337 ## - MEDIA TYPE
Media type term computer
Media type code c
Source rdamedia
338 ## - CARRIER TYPE
Carrier type term online resource
Carrier type code cr
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490 1# - SERIES STATEMENT
Series statement Lecture notes in computer science,
International Standard Serial Number 0302-9743 ;
Volume/sequential designation 3740
504 ## - BIBLIOGRAPHY, ETC. NOTE
Bibliography, etc Includes bibliographical references and index.
588 0# - SOURCE OF DESCRIPTION NOTE
Source of description note Print version record.
505 0# - FORMATTED CONTENTS NOTE
Formatted contents note Keynote Address I -- Processor Architecture for Trustworthy Computers -- Session 1A: Energy Efficient and Power Aware Techniques -- Efficient Voltage Scheduling and Energy-Aware Co-synthesis for Real-Time Embedded Systems -- Energy-Effective Instruction Fetch Unit for Wide Issue Processors -- Rule-Based Power-Balanced VLIW Instruction Scheduling with Uncertainty -- An Innovative Instruction Cache for Embedded Processors -- Dynamic Voltage Scaling for Power Aware Fast Fourier Transform (FFT) Processor -- Session 1B: Methodologies and Architectures for Application-Specific Systems -- Design of an Efficient Multiplier-Less Architecture for Multi-dimensional Convolution -- A Pipelined Hardware Architecture for Motion Estimation of H.264/AVC -- Embedded Intelligent Imaging On-Board Small Satellites -- Architectural Enhancements for Color Image and Video Processing on Embedded Systems -- A Portable Doppler Device Based on a DSP with High- Performance Spectral Estimation and Output -- Session 2A: Processor Architectures and Microarchitectures -- A Power-Efficient Processor Core for Reactive Embedded Applications -- A Stream Architecture Supporting Multiple Stream Execution Models -- The Challenges of Massive On-Chip Concurrency -- FMRPU: Design of Fine-Grain Multi-context Reconfigurable Processing Unit -- Session 2B: High-Reliability and Fault-Tolerant Architectures -- Modularized Redundant Parallel Virtual File System -- Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures -- A Fault-Tolerant Routing Strategy for Fibonacci-Class Cubes -- Embedding of Cycles in the Faulty Hypercube -- Session 3A: Compiler and OS for Emerging Architectures -- Improving the Performance of GCC by Exploiting IA-64 Architectural Features -- An Integrated Partitioning and Scheduling Based Branch Decoupling -- A Register Allocation Framework for Banked Register Files with Access Constraints -- Designing a Concurrent Hardware Garbage Collector for Small Embedded Systems -- Irregular Redistribution Scheduling by Partitioning Messages -- Session 3B: Data Value Predictions -- Making Power-Efficient Data Value Predictions -- Speculative Issue Logic -- Using Decision Trees to Improve Program-Based and Profile-Based Static Branch Prediction -- Arithmetic Data Value Speculation -- Exploiting Thread-Level Speculative Parallelism with Software Value Prediction -- Keynote Address II -- Challenges and Opportunities on Multi-core Microprocessor -- Session 4A: Reconfigurable Computing Systems and Polymorphic Architectures -- Software-Oriented System-Level Simulation for Design Space Exploration of Reconfigurable Architectures -- A Switch Wrapper Design for SNA On-Chip-Network -- A Configuration System Architecture Supporting Bit-Stream Compression for FPGAs -- Biological Sequence Analysis with Hidden Markov Models on an FPGA -- FPGAs for Improved Energy Efficiency in Processor Based Systems -- Morphable Structures for Reconfigurable Instruction Set Processors -- Session 4B: Interconnect Networks and Network Interfaces -- Implementation of a Hybrid TCP/IP Offload Engine Prototype -- Matrix-Star Graphs: A New Interconnection Network Based on Matrix Operations -- The Channel Assignment Algorithm on RP(k) Networks -- Extending Address Space of IP Networks with Hierarchical Addressing -- The Star-Pyramid Graph: An Attractive Alternative to the Pyramid -- Building a Terabit Router with XD Networks -- Session 5A: Parallel Architectures and Computation Models -- A Real Coded Genetic Algorithm for Data Partitioning and Scheduling in Networks with Arbitrary Processor Release Time -- D3DPR: A Direct3D-Based Large-Scale Display Parallel Rendering System Architecture for Clusters -- Determining Optimal Grain Size for Efficient Vector Processing on SIMD Image Processing Architectures -- A Technique to Reduce Preemption Overhead in Real-Time Multiprocessor Task Scheduling -- Session 5B: Hardware-Software Partitioning, Verification, and Testing of Complex Architectures -- Minimizing Power in Hardware/Software Partitioning -- Exploring Design Space Using Transaction Level Models -- Increasing Embedding Probabilities of RPRPs in RIN Based BIST -- A Practical Test Scheduling Using Network-Based TAM in Network on Chip Architecture -- Session 6A: Architectures for Secured Computing -- DRIL- A Flexible Architecture for Blowfish Encryption Using Dynamic Reconfiguration, Replication, Inner-Loop Pipelining, Loop Folding Techniques -- Efficient Architectural Support for Secure Bus-Based Shared Memory Multiprocessor -- Covert Channel Analysis of the Password-Capability System -- Session 6B: Simulation and Performance Evaluation -- Comparing Low-Level Behavior of SPEC CPU and Java Workloads -- Application of Real-Time Object-Oriented Modeling Technique for Real-Time Computer Control -- VLSI Performance Evaluation and Analysis of Systolic and Semisystolic Finite Field Multipliers -- Session 7: Architectures for Emerging Technologies and Applications I -- Analysis of Real-Time Communication System with Queuing Priority -- FPGA Implementation and Analyses of Cluster Maintenance Algorithms in Mobile Ad-Hoc Networks -- A Study on the Performance Evaluation of Forward Link in CDMA Mobile Communication Systems -- Session 8: Memory Systems Hierarchy and Management -- Cache Leakage Management for Multi-programming Workloads -- A Memory Bandwidth Effective Cache Store Miss Policy -- Application-Specific Hardware-Driven Prefetching to Improve Data Cache Performance -- Targeted Data Prefetching -- Session 9: Architectures for Emerging Technologies and Applications II -- Area-Time Efficient Systolic Architecture for the DCT -- Efficient VLSI Architectures for Convolution and Lifting Based 2-D Discrete Wavelet Transform -- A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures -- Implementation and Analysis of TCP/IP Offload Engine and RDMA Transfer Mechanisms on an Embedded System.
520 ## - SUMMARY, ETC.
Summary, etc. On behalf of the ProgramCommittee, we are pleased to present the proceedings of the 2005 Asia-Paci?c Computer Systems Architecture Conference (ACSAC 2005) held in the beautiful and dynamic country of Singapore. This conference was the tenth in its series, one of the leading forums for sharing the emerging research?ndings in this?eld. In consultation with the ACSAC Steering Committee, we selected a - member Program Committee. This Program Committee represented a broad spectrum of research expertise to ensure a good balance of research areas, - stitutions and experience while maintaining the high quality of this conference series. This year's committee was of the same size as last year but had 19 new faces. We received a total of 173 submissions which is 14% more than last year. Each paper was assigned to at least three and in some cases four ProgramC- mittee members for review. Wherever necessary, the committee members called upon the expertise of their colleagues to ensure the highest possible quality in the reviewing process. As a result, we received 415 reviews from the Program Committee members and their 105 co-reviewers whose names are acknowledged inthe proceedings. Theconferencecommitteeadopteda systematicblind review process to provide a fair assessment of all submissions. In the end, we accepted 65 papers on a broad range of topics giving an acceptance rate of 37.5%. We are grateful to all the Program Committee members and the co-reviewers for their e?orts in completing the reviews within a tight schedule.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computer architecture
Form subdivision Congresses.
9 (RLIN) 16686
650 #6 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Ordinateurs
General subdivision Architecture
Form subdivision Congrès.
9 (RLIN) 19224
650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element COMPUTERS
General subdivision Systems Architecture
-- General.
Source of heading or term bisacsh
9 (RLIN) 18220
650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Informatique.
Source of heading or term eclas
9 (RLIN) 14930
650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computer architecture.
Source of heading or term fast
Authority record control number (OCoLC)fst00872026
9 (RLIN) 2947
650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Computerarchitektur
Source of heading or term gnd
9 (RLIN) 22328
650 17 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Architecture informatique.
Source of heading or term rasuqam
9 (RLIN) 21916
650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name as entry element Système informatique.
Source of heading or term rasuqam
9 (RLIN) 19608
655 #2 - INDEX TERM--GENRE/FORM
Genre/form data or focus term Congress
9 (RLIN) 11670
655 #7 - INDEX TERM--GENRE/FORM
Genre/form data or focus term Conference papers and proceedings.
Source of term fast
Authority record control number (OCoLC)fst01423772
9 (RLIN) 6065
655 #7 - INDEX TERM--GENRE/FORM
Genre/form data or focus term Conference papers and proceedings.
Source of term lcgft
9 (RLIN) 6065
655 #7 - INDEX TERM--GENRE/FORM
Genre/form data or focus term Actes de congrès.
Source of term rvmgf
9 (RLIN) 609890
655 #7 - INDEX TERM--GENRE/FORM
Genre/form data or focus term Kongress.
Source of term swd
9 (RLIN) 2843
655 #7 - INDEX TERM--GENRE/FORM
Genre/form data or focus term Singapur (2005)
Source of term swd
9 (RLIN) 28141
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Srikanthan, Thambipillai.
9 (RLIN) 28246
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Xue, Jingling,
Dates associated with a name 1962-
-- https://id.oclc.org/worldcat/entity/E39PCjvJgjXF7K8FYyxqvJGVwd
9 (RLIN) 18222
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Chang, Chip-Hong.
9 (RLIN) 28247
776 08 - ADDITIONAL PHYSICAL FORM ENTRY
Relationship information Print version:
Main entry heading ACSAC 2005 (2005 : Singapore).
Title Advances in computer systems architecture.
Place, publisher, and date of publication Berlin ; New York : Springer, 2005
International Standard Book Number 3540296433
-- 9783540296430
Record control number (DLC) 2005934301
-- (OCoLC)62185932
830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE
Uniform title Lecture notes in computer science ;
Volume number/sequential designation 3740.
International Standard Serial Number 0302-9743
856 40 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier <a href="https://link.springer.com/10.1007/11572961">https://link.springer.com/10.1007/11572961</a>
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