Amazon cover image
Image from Amazon.com

Neural networks and systolic array design [electronic resource] / editors, David Zhang, Sankar K. Pal.

Contributor(s): Material type: TextTextSeries: Series in machine perception and artificial intelligence ; v. 49.Publication details: River Edge, N.J. : World Scientific, c2002.Description: 1 online resource (xiv, 405 p.) : illISBN:
  • 9789812778086 (electronic bk.)
  • 981277808X (electronic bk.)
Subject(s): Genre/Form: Additional physical formats: Print version:: Neural networks and systolic array design.DDC classification:
  • 006.3/2 22
LOC classification:
  • QA76.87 .N47914 2002eb
Online resources:
Contents:
Ch. 1. Neural networks and systolic arrays: models and integration / D. Zhang and S.K. Pal -- Ch. 2. Systolic array methodology for a neural model to solve the mixture problem / R.M. Pérez ... [et al.] -- Ch. 3. Morphological endmember identification and its systolic array design / P.L Aguilar ... [et al.] -- Ch. 4. MANTRA I: a systolic array for neural computation / M.A. Viredaz and P. Ienne -- Ch. 5. Mixed-signal neuro-fuzzy processor implementations: sequential architectures and circuit-level description / J. Madrenas and E. Alarcón -- Ch. 6. CMAC neural networks and systolic implementation / B.D. Lui, Y.H. Kuo and J.S. Ker -- Ch. 7. Quadrant interlocking factorization on systolic and wavefront array processors / M.P. Bekakos, O.B. Efremides and D.J. Evans -- Ch. 8. Systolic S.O.M. neural network for hyperspectral image classification / P. Martinez ... [et al.]
Ch. 9. Optimizing and learning algorithm for feedforward neural networks and its implementation by systolic array / P.B. Burgos -- Ch. 10. Parallel ANN architecture for fuzzy patterns / D. Zhang and S.K. Pal -- Ch. 11. Pipelined systolic arrays for time-delay neural networks / D. Zhang and S.K. Pal -- Ch. 12. An integrated intelligent classification engine (I[superscript 2]CE for biosignal engineering / A.N. Kastania and M.P. Bekakos -- Ch. 13. Multiplierless designs for artificial neural networks / H.K. Kwan -- Ch. 14. A VLSI system for intelligent decision making in real-time / N. Ranganathan and M.I. Patel -- Ch. 15. Reconfigurable hardware systolic array for real-time compartmental modeling of large-scale artificial nervous systems / M. Korkin -- Ch. 16. Implementing and mapping ANNs on reconfigurable mesh massively parallel architectures / W.N. Li and J.J. Jenq.
Holdings
Item type Current library Collection Call number Status Date due Barcode Item holds
eBook eBook e-Library EBSCO Computers Available
Total holds: 0

Includes bibliographical references and index.

Ch. 1. Neural networks and systolic arrays: models and integration / D. Zhang and S.K. Pal -- Ch. 2. Systolic array methodology for a neural model to solve the mixture problem / R.M. Pérez ... [et al.] -- Ch. 3. Morphological endmember identification and its systolic array design / P.L Aguilar ... [et al.] -- Ch. 4. MANTRA I: a systolic array for neural computation / M.A. Viredaz and P. Ienne -- Ch. 5. Mixed-signal neuro-fuzzy processor implementations: sequential architectures and circuit-level description / J. Madrenas and E. Alarcón -- Ch. 6. CMAC neural networks and systolic implementation / B.D. Lui, Y.H. Kuo and J.S. Ker -- Ch. 7. Quadrant interlocking factorization on systolic and wavefront array processors / M.P. Bekakos, O.B. Efremides and D.J. Evans -- Ch. 8. Systolic S.O.M. neural network for hyperspectral image classification / P. Martinez ... [et al.]

Ch. 9. Optimizing and learning algorithm for feedforward neural networks and its implementation by systolic array / P.B. Burgos -- Ch. 10. Parallel ANN architecture for fuzzy patterns / D. Zhang and S.K. Pal -- Ch. 11. Pipelined systolic arrays for time-delay neural networks / D. Zhang and S.K. Pal -- Ch. 12. An integrated intelligent classification engine (I[superscript 2]CE for biosignal engineering / A.N. Kastania and M.P. Bekakos -- Ch. 13. Multiplierless designs for artificial neural networks / H.K. Kwan -- Ch. 14. A VLSI system for intelligent decision making in real-time / N. Ranganathan and M.I. Patel -- Ch. 15. Reconfigurable hardware systolic array for real-time compartmental modeling of large-scale artificial nervous systems / M. Korkin -- Ch. 16. Implementing and mapping ANNs on reconfigurable mesh massively parallel architectures / W.N. Li and J.J. Jenq.

Description based on print version record.

Powered by Koha