TY  - BOOK
AU  - Camurati,Paolo
AU  - Eveking,Hans
ED  - Advanced Research Working Conference on Correct Hardware Design Methodologies
TI  - Correct Hardware Design and Verification Methods: IFIP WG 10.5 Advanced Research Working Conference, CHARME '95 Frankfurt/Main, Germany, October 2-4, 1995 Proceedings 
T2  - Lecture Notes in Computer Science,
SN  - 9783540455165
AV  - TK7874 .A3353 1995
U1  - 621.39/5 20
PY  - 1995///
CY  - Berlin, Heidelberg
PB  - Springer-Verlag
KW  - Engineering
KW  - Data transmission systems
KW  - Software engineering
KW  - Logic design
KW  - Electronics
KW  - Computer-aided design
KW  - Congresses
KW  - Integrated circuits
KW  - Verification
KW  - Very large scale integration
KW  - Design and construction
KW  - Data processing
KW  - Ingénierie
KW  - Génie logiciel
KW  - Structure logique
KW  - Électronique
KW  - Conception assistée par ordinateur
KW  - Congrès
KW  - Circuits intégrés
KW  - Vérification
KW  - engineering
KW  - aat
KW  - fast
KW  - Conference papers and proceedings
N1  - Includes bibliographical references; What if model checking must be truly symbolic / H. Hungar [and others] -- Automatic verification of the SCI cache coherence protocol / U. stern, D.L. Dill -- Describing and verifying synchronous circuits with the Boyer-Moore theorem prover / L. Pierre -- Problems encountered in the machine-assisted proof of hardware / P. Curzon -- Formally embedding existing high level synthesis algorithms / D. Eisenbiegler, R. Kumar -- Formal design of a class of computers / L.G. Wang, M. Mendler -- Symbolic analysis and verification of CPA descriptions / M.C. McFarland, T.J. Kowalski -- A foundation for formal reuse of hardware / A.C.V. de Melo, H. Barringer -- State enumeration with abstract descriptions of state machines / F. Corella [and others] -- Transforming boolean relations by symbolic encoding / G. Cabodi [and others] -- Design error diagnosis in sequential circuits / A. Wahba, D. Borrione -- Timing analysis of asynchronous circuits using timed automata / O. Maler, A. Pnueli -- Improved probabilistic verification by hash compaction / U. Stern, D.L. Dill -- Formal support for the ELLA hardware description language / H. Barringer, B. Monahan, A. Williams -- Verifying hardware components within JACK / R. De Nicola [and others] -- Language containment of non-deterministic [omega]-automata / S. Taşiran, R. Hojati, R.K. Brayton -- A partial-order approach to the verification of concurrent systems : checking liveness properties / D. Bolignano -- Semantics of a verification-oriented subset of VHDL / D. Déharbe, D. Borrione -- Reasoning about VHDL using operational and observational semantics / K.G.W. Gossens -- A symbolic relation for a subset of VHDL '87 descriptions and its application to symbolic model checking / E. Encrenaz
N2  - This book constitutes the refereed proceedings of the IFIP WG10.5 Advanced Research Working Conference on Correct Hardware Design Methodologies, CHARME '95, held in Frankfurt, Germany, in October 1995. The 20 revised full papers presented were carefully selected by the program committee and address all current aspects of research and advanced applications in the field of formal verification of hardware. Among the topics covered are model checking, theorem proving, formally verified synthesis, process algebras, finite state systems, verification environments, language containment, and VHDL
UR  - https://link.springer.com/10.1007/3-540-60385-9
ER  -