Formal methods in computer-aided design : 4th international conference, FMCAD 2002, Portland, OR, USA, November 6-8, 2002 : proceedings / Mark D. Aagaard, John W. O'Leary (eds.).

Includes bibliographical references and index.

This book constitutes the refereed proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design, FMCAD 2002, held in Portland, OR, USA in November 2002. The 23 revised full papers presented were carefully reviewed and selected from 47 submissions. The book offers topial sections on abstraction, symbolic simulation, model checking, microprocessor specification and verification, decision procedures, verification techniques and methodology, hardware description languages, and prototyping and synthesis.

Abstraction -- Abstraction by Symbolic Indexing Transformations -- Counter-Example Based Predicate Discovery in Predicate Abstraction -- Automated Abstraction Refinement for Model Checking Large State Spaces Using SAT Based Conflict Analysis -- Symbolic Simulation -- Simplifying Circuits for Formal Verification Using Parametric Representation -- Generalized Symbolic Trajectory Evaluation -- Abstraction in Action -- Model Checking: Strongly-Connected Components -- Analysis of Symbolic SCC Hull Algorithms -- Sharp Disjunctive Decomposition for Language Emptiness Checking -- Microprocessor Specification and Verification -- Relating Multi-step and Single-Step Microprocessor Correctness Statements -- Modeling and Verification of Out-of-Order Microprocessors in UCLID -- Decision Procedures -- On Solving Presburger and Linear Arithmetic with SAT -- Deciding Presburger Arithmetic by Model Checking and Comparisons with Other Methods -- Qubos: Deciding Quantified Boolean Logic Using Propositional Satisfiability Solvers -- Model Checking: Reachability Analysis -- Exploiting Transition Locality in the Disk Based Mur? Verifier -- Traversal Techniques for Concurrent Systems -- Model Checking: Fixed Points -- A Fixpoint Based Encoding for Bounded Model Checking -- Using Edge-Valued Decision Diagrams for Symbolic Generation of Shortest Paths -- Verification Techniques and Methodology -- Mechanical Verification of a Square Root Algorithm Using Taylor's Theorem -- A Specification and Verification Framework for Developing Weak Shared Memory Consistency Protocols -- Model Checking the Design of an Unrestricted, Stuck-at Fault Tolerant, Asynchronous Sequential Circuit Using SMV -- Hardware Description Languages -- Functional Design Using Behavioural and Structural Components -- Compiling Hardware Descriptions with Relative Placement Information for Parametrised Libraries -- Prototyping and Synthesis -- Input/Output Compatibility of Reactive Systems -- Smart Play-out of Behavioral Requirements.

English.